Speaker: Tushit Jain
Traditional algorithms used in computer aided design (CAD) of complex SoCs require an ever-increasing number of resources in terms of designers, compute, licenses and time. These limitations of algorithm-driven CAD prevent chip design from scaling to higher complexity while maintaining optimal power, performance and area (PPA). In this talk, we explore the applications of Machine Learning or data-driven CAD to the area of VLSI/SoC design to help scale SoCs to higher complexities.
Tushit Jain is a Senior Director in Machine Learning Research at Qualcomm. He works on building Machine Learning based tools to improve all aspects of the hardware design process ranging from Design, Verification and Physical Design. The AI/ML models that he and his team have built have been successfully deployed on taped-out chips and have helped improve power, performance, area of these chips while also reducing the engineering effort to build and productize chips at Qualcomm.