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Location: DESE Auditorium
Department of Electronic Systems Engineering (ESE)
Lecture Announcement
Title: Post –Moore’s Law Electronics: An Unparalleled Opportunity for India’s Scientific, Engineering and Industrial Organizations – Part I
Speaker: Prof. Rao R. Tummala, Georgia Institute of Technology, Atlanta, GA 30332 USA, and
Satish Dhawan Visiting Chair Professor, Indian Institute of Science, Bangalore, India
Date and time: 29 October (Tuesday), 4 PM
Venue: ESE Auditorium (1st floor)
Abstract:
Moore’s law has been the driving engine for science, technology, manufacturing, hardware, software, systems, and applications, contributing to the prosperity of thousands of individuals, 100’s corporations and dozens of countries. As Moore’s Law begins to come to an end, for not only fundamental reasons but also for computing performance, power, cost, and investments, it is becoming clear that a different vision for electronics systems must emerge. So, while transistor integration to a 20 billion-transistor-chip on individual ICs so far was the basis of Moore’s Law for ICs, this can be extended in 2.5D and 3D by means of new paradigms in electronic and optoelectronic interconnections, in the short term. This is referred to as Moore’s Law for Packaging or interconnections. Just like Moore’s Law has both the doubling of transistors and simultaneous cost reduction from node to node, every 18-24 months, Moore’s Law for Packaging can do the same. Interconnections have been driven by computing systems and within computing systems, between logic and memory, consistent with Von Neumann’s architecture . The new era of artificial intelligence mimicking the human brain, with several orders better computer performance than with the current electronics, is yet another reason for the end of Moore’s Law. The human brain is the ultimate system packaging for the highest performance in the smallest size with the lowest power. The human brain is the new standard in packaging density, and computing performance-power efficiency. This is more than current 3D electronic architectures. A typical human brain has about 90 billion nerve cells interconnected by trillions of synapses providing trillions of pathways for the brain to process the information along with petabyte memory. New Moore’s Law, therefore, must duplicate this architecture.
The packaging or I/Os has historically evolved dramatically from dual-in-line ceramic packages in the 1970s with 16 I/Os, plastic quadflatpack packages in 1980s with 64 I/Os, ceramic packages in 1990s with more than 10,000 I/Os, organic laminate packages in excess of 20,000 I/Os and silicon packages approaching 200,000 I/Os. Artificial intelligence mimicking human brain may need several orders of magnitude. Currently, the best Moore’s Law for packaging is with wafer-based silicon packaging. But silicon-based packaging has many limitations at the material, device, circuit, and system levels.
The seminar describes a vision for post Moore’s Law Electronics from Moore’s Law for ICs to electronic and photonic interconnections and eventually to DNA and quantum computing. Post Moore’s Law electronics is highly interdisciplinary, requiring a team of scientists and engineers to work together from electrical, mechanical, thermal, optical, bio and nanomaterials, and chemical process disciplines. The Post-Moore’s Law electronics provides a new opportunity for India to be a global player, in contrast to old Moore’s Law
Bio:
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor Emeritus at Georgia Tech in USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the industry’s first plasma display and industry’s first 100- chip integrated and ultra-high performance computing modules with leading-edge interconnections, flipchip assembly and liquid cooling, now called 2.5D. He is the father of Low-temperature co-fired ceramic (LTCC) and System-on-Package (SOP) technologies. As an educator, Prof. Tummala was instrumental in setting up the largest academic Center in System-On-Package vision, in contrast to System-on-Chip (SOC) by the industry for electronic systems, funded by NSF as the first and only NSF National Engineering Research Center in the US in Packaging and interconnections at Georgia Tech. The Center he started with its integrated approach to research, education and industry collaborations produced more than 1000 engineers at Ph.D. and MS levels and collaborated with more than 200 companies in US, Europe, Japan, Korea, Taiwan, and China. He received many industry, academic and professional society awards including Distinguished Alumni from University of Illinois and Indian Institute of Science, in addition to the highest Faculty award from Georgia Tech—The Distinguished Faculty. He published 800 technical papers and invented many technologies that resulted in over 100 US patents. He wrote the first modern textbook in packaging, Microelectronics Packaging Handbook (1988); wrote the 1st undergrad textbook, Fundamentals of Microsystem Packaging (2001); and the 1st book introducing the concept of SOP, Introduction to System-on-Package (2006). He was Past President OF IEEE CPMT and IMAPS Societies. He is an IEEE Fellow and member of the National Academy of Engineering in the US and India. He is a graduate and Distinguished Alumni of the Indian Institute of Science.
ALL ARE WELCOME
(High tea after the talk)
