The security of modern cryptographic protocols relies on the computational hardness of mathematical problems such as integer factorization and discrete logarithm. While these problems are intractable for even the most powerful classical supercomputers, they can be solved in polynomial time using Shor’s algorithm using large-scale fault-tolerant quantum computers. This makes our current public key cryptography standards such as RSA and ECC vulnerable to future quantum adversaries, thus motivating the development of post-quantum cryptography (PQC) algorithms based on new primitives such as lattices, isogenies, codes, etc. Researchers at the Secure Intelligent and Efficient Systems (SINESys) Lab in the Department of Electronic Systems Engineering (ESE), IISc are working on the efficient and secure implementation of emerging PQC algorithms. The group, led by Dr. Utsav Banerjee, has developed various custom hardware accelerators for upcoming PQC standards along with demonstration of RISC-V-based hardware-software co-design of PQC for resource-constrained embedded applications.
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