Design of system integrity protection schemes using synchrophasor measurements

Location: MMCR

Title – Design of system integrity protection schemes using synchrophasor measurements

Venue: MMCR, EE

Date and Time: 23rd October, Wednesday, 3.30p.m. to 4.30p.m.

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Abstract – The talk will focus on controlled islanding and early detection of voltage instability in power systems. In controlled islanding, out-of-step prediction, early cutset determination and a transfer tripping scheme will be discussed. In another application, a unified early warning scheme (EWS) for detecting voltage instability will be presented. The approach shows that, by extrapolating real-time trends in PMU time series, limit violations in bus voltages and generator reactive power output can be estimated well in advance.

Speaker bio –
Akhil Raj obtained his B.Tech in Electrical and Electronics Engineering, 2012 from VIT University, Vellore and M.Tech. in Power Systems Engineering, 2014 from the National Institute of Technology (NIT) Warangal. He is currently pursuing his Ph.D. in Electrical Engineering from Indian Institute of Technology, Bombay. His areas of interest are Power System Protection and WAMS applications in power systems.

Aditya Nadkarni obtained his B.Tech in Electrical Engineering from VJTI (Mumbai University) in 2010, and M.S. in Power Systems, from Arizona State University, USA in 2013. He is currently pursuing his Ph.D. in Electrical Engineering from Indian Institute of Technology, Bombay. His areas of interest are design of real-time data-analytics and power system optimization.

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All are welcome.

Gurunath Gurrala