Prof. Mayank Shrivastava is a faculty member at the Indian Institute of Science, Bangalore, and co-founder of AGNIT Semiconductors Pvt. Ltd. He received his Ph.D. degree from the Indian Institute of Technology Bombay (2010). For his PhD work, he received Excellence in Research award and the Industrial Impact award from IIT Bombay in 2010. He is among the first recipients of the Indian section of the American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). He is also an Editor of IEEE Transactions on Electron Devices. Besides, he is an IEEE Electron Device’s Society (EDS) Distinguished Lecturer and an elected member to the IEEE EDS Board of Governors. He is the recipient of prestigious DST Swarnjayanti Fellowship (2021), Abdul Kalam Technology Innovation National Fellowship from INAE-SERB (2021) and VASVIK award (2021). He has received several other national awards and honors of high repute, like the National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award – 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award – 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Ministry of Electronics & Information Technology (MeitY), Young Faculty Fellowship. Besides, he received best paper awards from several international conferences like Intel Corporation Asia academic forum, VLSI design Conference and EOSESD Symposium. Prof Shrivastava broadly works on applications of emerging materials like Gallium Nitride (GaN), atomically thin two-dimensional materials like Graphene and TMDCs, in electronic and electro-optic devices working closer to its fundamental limits (like the ability to handle extreme powers, ability to work at THz like ultra-high frequencies, or ability to compute information in unconventional ways). Currently, his group is developing few-atom thick devices & circuits, GaN-based ultra-high-power devices with high reliability, and devices/circuits for operation at THz frequencies. Besides, his group also works on developing novel ESD and High Voltage device concepts in advanced CMOS nodes. He had held visiting positions in Inﬁneon Technologies, Munich, Germany, from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Inﬁneon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; Intel Corp, Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined the Indian Institute of Science as a faculty member in the year 2013. Prof Shrivastava’s work has resulted in over 190 peer-reviewed publications and 45 patents. Most of these patents are either licensed by semiconductor companies or are in use in their products.
Prof. Shrivastava’s group works on (i) probing the fundamental challenges or roadblocks in enabling the next generation nanoelectronics and power semiconductor device technologies and (ii) translating the new science discovered into better / industrially relevant semiconductor technologies.
On the nanoelectronics front, in the past five years, his group has primarily focused on graphene and other 2D materials, such as transition metal dichalcogenide (TMDs), based technologies. Despite the remarkable potential of these next-generation platforms, these technologies were plagued by several fundamental showstoppers, such as (i) how to interface/connect these 2-dimensional materials with a 3-dimensional world with interface resistance close to quantum limits, (ii) how to develop reliable transistors with performance close to its theoretical limits, and (iii) how to enable a p-channel transistor without which industries couldn’t build CMOS circuits or 2D chips. Prof. Shrivastava’s works probed the quantum chemistry of 3D (metal) – 2D (graphene/TMDs) interfaces, which enabled him to develop novel methods to engineer the contacts (metal-2D interface) for all key 2D channels while achieving record low contact resistance crossing the quantum limit predicted earlier. Besides, his group probed the root cause behind several other performance and reliability showstoppers, such as current-voltage hysteresis behavior, lower mobilities, implications of point defects, defect annealing, time-dependent breakdown, e-field assisted material reconfiguration, etc. and developed physical insights into these phenomena using detailed experiments and first principal methods. These insights enabled the nominee to devise methods to address performance and reliability showstoppers in 2D semiconductor technologies. It resulted in record high-performance transistors using all the key 2D channels (such as graphene, MoS2, WS2, MoSe2 and WSe2) with engineered contacts. Finally, his group could also address the quest for enabling p-channel conduction, which is essential for developing p-type (or complimentary) transistors. A missing p-channel transistor has been the showstopper for semiconductor industries to demonstrate CMOS chips using 2D semiconductors. The experimental and computational probes enabled Prof. Shrivastava’s group to selectively engineer mid-gap states to develop p-channel and n-channel transistors in the same chip – enabling the CMOS operation for the first time with record-high performance. These findings and technology modules also enabled his group to demonstrate better synaptic devices using these 2D materials for on-chip neuromorphic applications.
On the power semiconductor device front, in the past five years, Prof. Shrivastava’s group has primarily worked on Gallium Nitride (GaN) HEMTs and Si LDMOS devices with a quest to address the performance and reliability showstoppers to push their operations closer to theoretical limits. As GaN HEMTs are normally-ON by default, the fundamental question was how to enable a normally-OFF HEMT, which is a must for power electronics applications. Besides, GaN HEMTs suffered several reliability challenges, primarily attributed to lack of fundamental insights into phenomena such as dynamic ON-resistance behaviour, breakdown mechanism, interplay of various trap/defect states, time dependent failure, and physical mechanisms governing safe operating area, electrostatic discharge behavior, etc. Using detailed experimentations, his group probed these fundamental performance and reliability showstoppers and developed physical insights explaining the root cause of the problem. These insights helped his group devise methods to engineer HEMTs for improved reliability and performance. Besides, his group discovered a unique way to engineer the gate stack of these HEMT devices – by using a p-type dielectric – which enabled normally-OFF operation. These explorations enabled Prof. Shrivastava’s group to demonstrate high performance – highly reliable (and India’s first) enhancement mode (e-mode) HEMT device and GaN diodes for next-generation power electronics applications and monolithically integrated power electronics concepts.
On the Si LDMOS front, Prof. Shrivastava’s has been instrumental in developing and enabling integrated Si LDMOS devices, which in today’s System on Chips (SoCs) and Power SoCs (Automotive ICs) covers ~40% and ~70% of the chip area, respectively. Since 1970 various integrated high-power Si devices have been proposed for such applications. However, they used to fail under high current switching conditions, which seriously hampered the usefulness of these devices for advanced SoC products. The physical cause for such failures was not known to scientists before. For example, various groups speculated that high current failures in LDMOS devices are stochastic in nature; however, nominee’s work revealed the deterministic and unified nature of these failures across various types of integrated Si LDMOS devices. These insights enabled the nominee to invent a new class of robust & high-performance LDMOS devices, which can be found in advanced SoCs today. His research also changed the perception that robustness and performance cannot be achieved together, particularly for the high power-high frequency application. Going a step further, he invented and designed the first high-power devices for FinFET technology. SoC design in these very advanced CMOS technologies was not expected soon. However, recent device inventions resulting from his work have enabled semiconductor industries to design and manufacture SoC in FinFET and related CMOS nodes.