This work involves design and implementation of a low cost, open-source, heterogeneous, resource-constrained hardware platform called “Parallella” as a measurement device for edge computing applications research in smart grid. The hardware architecture of Parallella is unique for its multitude of edge compute resources in the form of a Zynq SoC (dual-core ARM + FPGA) and a 16 core co-processor called Epiphany.
We have optimised the cost of IED development to approximately INR 60,000 ($760). Parallella is an open platform and incorporates an industrial Zynq platform at less than 5 W power. We believe it is an excellent choice for even commercial product development at an affordable cost. We have demonstrated a multi-functional IED design to showcase the capabilities of the platform. A custom I/O board has been developed for Parallella, which can be interfaced with external peripherals for measurements. One such daughter board is an analog sensing board (see Figure), which can measure voltages of all the 3 phases and 4 line currents using a 16-bit synchronous ADC set at 64 kHz. The ADC samples are synchronized to PPS time clock of a GPS unit for providing global time reference. This captured 7-channels raw waveform data is sent to a cloud server over a bandwidth-limited communication channel using a custom anomaly-aware data compression algorithm implemented on the ARM. A Phasor measurement algorithm using Teager Energy Operator is implemented on the FPGA. A parallel power quality measurement algorithm is implemented on the Epiphany. The obtained measurements are found to be comparable to a commercial power analyzer (see Figure).
This is joint work with Ashish Joglekar, Puneet Kumar, Francis C Joseph, T.S. Kiran, and K.R. Sahasranand.
Ashish Joglekar, Gurunath Gurrala, Puneet Kumar, Francis C Joseph, T.S. Kiran, K.R. Sahasranand and Himanshu Tyagi, “Open Source Heterogeneous Constrained Edge Computing Platform for Smart Grid Measurements,” To appear in: IEEE Transactions on Instrumentation & Measurement, 2021.